計(jì)算結(jié)構(gòu) 3：計(jì)算機(jī)組織培訓(xùn)

Pipelined Beta: pipelined execution of instructions, data and control hazards, resolving hazards using bypassing, stalling and speculation.

Virtual Memory: extending the memory hierarchy, paging using hierarchical page maps and look-aside buffers,

contexts and context switching, integrating virtual memories with caches.

Operating Systems: processes, interrupts, time sharing, supervisor calls.

Devices and Interrupts: device handlers asynchronous I/O,

stalling supervisor calls, scheduling, interrupt latencies, weak and strong priority systems.

Processes, Synchronization and Deadlock: inter-process communication,

bounded buffer problem, semaphores for precedence and mutual exclusion, semaphore implementation, dealing with deadlock.

Interconnect: the truth about wires, point-to-point vs. shared interconnect, communication topologies.

Parallel Processing: instruction-, data- and thread-level parallelism, Amdahl’s Law, cache coherency.

Labs: optimizing your Beta design for size and speed, emulating instructions, extending a simple time-sharing operating system.